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When the Z80 wishes to access an IO port, it places the port address on the address bus exactly as it does when accessing memory. On the 48K and 128K Spectrums, this causes delays to IO as the ULA halts the processor. On the +3 Spectrum, no contention occurs as the +3 ULA applies contention only when the Z80's MREQ line is active, which it is not during an IO operation. Two effects can occur here:

  1. If the port address has its low bit reset, the ULA halts the processor to supply the result.
  2. If the port being accessed is between 0x4000 and 0x7fff, this "looks like" an access to contended memory to the ULA and it again halts the processor. Contention is also applied if the port address is between 0xc000 and 0xffff on a 128K Spectrum with a contended RAM bank paged into that address range.[1][2]

The combination of these two effects leads to the following pattern:

High byte in 0x40 (0xc0) to 0x7f (0xff)? Low bit Contention pattern
No Reset N:1, C:3
No Set N:4
Yes Reset C:1, C:3
Yes Set C:1, C:1, C:1, C:1

The "Contention pattern" shows the sequence of (non-)contention which occurs: an entry of "N:x" means that the Z80 simply continues for x tstates, while "C:x" means that the Z80 is halted for the same number of tstates as with a normal contended memory access, before continuing for x tstates.