Talk:Bmsce ec/Manuals/VHDL

1)basic gates

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gates is   Port ( a : in std_logic;           b : in std_logic;           c : out std_logic;           d : out std_logic;           e : out std_logic;           f : out std_logic;           g : out std_logic;           h : out std_logic); end gates;

architecture Behavioral of gates is

begin c<=a and b;	 d<= a nand b;	  e <= a or b;	  f <= a nor b;	  g<= a xor b;	  h <= a xnor b; end Behavioral;